1. Field of the Invention
The present invention relates to the field of integrated circuit memory; more specifically, it relates to a method and circuit for dynamically changing the read margin of a memory array.
2. Background of the Invention
High performance microprocessors are designed to operate at high frequency and high voltage in high performance mode. High performance microprocessors utilize internal high performance self-timed cache memory to minimize the time required to access instructions or data as well as self-timed general-purpose memory. In battery-operated devices such as notebook computers, personal computers, handheld personal digital assistants (PDAs) and cell phones, utilizing high performance microprocessors and self-timed memories, the power consumed the device can be significant and low power modes would be highly desirable. However, current self-timed memories designed for high performance operation present signal timing problems in low power mode, precluding low power operation of the microprocessors. The same problem exists for high performance devices utilizing general-purpose memory designed for high performance.
Therefore, there is a need for a method for reducing the power consumption of microprocessors containing onboard memories as well as reducing the power consumption of general-purpose memories by adapting the memories to support operation at low voltages.